Chemical mechanical polishing/planarization (CMP) is a key process for smoothing surfaces of semiconductor wafers through both chemical etching and physical abrasion. A semiconductor wafer is mounted onto a polishing head, which rotates during a CMP process. The rotating polishing head presses the semiconductor wafer against a rotating polishing pad. Slurry containing chemical etchants and colloid particles is applied onto the polishing pad. Irregularities on the surface are removed resulting in planarization of the semiconductor wafer.
Complementary metal oxide semiconductor (CMOS)transistors are building blocks for integrated circuits, and CMOS devices continue to be scaled to smaller sizes for advanced performance targets. CMOS technology includes N-type metal oxide semiconductor (NMOS) and P-type metal oxide semiconductor (PMOS) transistors.
A CMOS transistor generally comprises a semiconductor substrate, a channel layer above the semiconductor substrate, a gate oxide layer and a gate stack above the channel layer, and source and drain diffusion regions in the surface of the semiconductor substrate. Contacts are made to the gate stack, and to both the source and drain regions of the transistor. With the advent of high-k dielectric materials as the gate insulating layer in the CMOS process, metal gates or metal layers can be used in the devices.